1. Field of the Invention
The present invention relates to a sample-hold circuit used, for example, for an analog digital converter or a wireless communication receiving circuit. More specifically, the present invention relates to a current switching source-follower-type sample-hold circuit wherein droop, namely a variation in a hold voltage caused by the leakage current of a transistor, and feed through, namely an influence of an input analog voltage on the hold voltage during a hold period, can be reduced.
2. Description of the Related Art
FIG. 1 is a circuit diagram according to a first example of the prior art of a sample-hold circuit of the current switching source-follower-type. This first example sample-hold circuit is functionally classified into: a preamplifier on the leftmost side, namely, the preamplifier as the section preceding the transistor 23, to the gate of which the potential V1 is applied; a core section of the sample-hold circuit comprising transistors 21 to 24 and a capacitor 25; and an output section comprising transistors 26 and 27.
The preamplifier comprises: transistors 11 and 12, to the gates of which the inverted signal RF of a sample signal (input analog signal) RF and the sample signal RF are input respectively; a transistor 13 comprising a current source I1; two resistors 15 and 16 which connect the drain terminals of the transistors 11 and 12 to the potential VDD (GND); and resistors 17 and 18 which connect the source terminals of the transistors 11 and 12 and the drain terminal of the transistor 13. The preamplifier amplifies the sample signal and outputs the amplification result to the core section from the output pin, as the drain terminal, of transistor 11.
The core section comprises: transistors 21 and 22, to the gate terminals of which the sample clock signal CLK and the inverted signal CLK are applied respectively; a transistor 23, to the gate terminal of which the output V1 of the preamplifier is applied, which is connected between VDD (GND) and the transistor 21; a transistor 24, which is connected to the source terminals of the transistors 21 and 22 and operates as the current source I2; and a capacitor 25 which is inserted in parallel between the drain and source of the transistors 23.
The sample-hold circuit in its entirety is called a current switching source-follower-type because, in the core section, the current source current I2 is switched and flows between the transistors 21 and 22 according to the value of the clock signal CLK, and the transistors 21 and 23 comprisea source-follower circuit.
During the sampling period wherein the sample clock CLK is “H”, the current source current I2 flows through the source-follower circuit, and as a result, the voltage across the capacitor 25 varies according to the value of the sample signal (input analog signal).
In contrast, during the hold period wherein the sample clock CLK is “L”, the current source current I2 is switched to the transistor 22-side, and this current flows into the resistor 15, out of the load resistors 15 and 16 of a differential transistor pair, transistors 11 and 12, which comprise the preamplifier. If the value of the resistor 15 is R1, the potential V1 during the hold period is lowered by “R1×I2” from the value immediately before the hold period by increasing the current flowing into the resistor R1 by I2. Thus, the transistor 23 which had been ON up until this point is turned OFF, and as a result, the charge stored in the capacitor 25 is retained and the voltage at both ends thereof is held. The held voltage is applied to an external section as the hold output via the transistor 26.
However, in the first example of the prior art, if the potential of the sample signal, namely the input analog signal, varies during the hold period, this variation affects the gate potential V1 of the transistor 23 via the transistor 11, and if the potential V1 rises, it may cause an increase in the sub-threshold current or cause the transistor to change from OFF to ON in the worst case. The leakage current of the transistor 23 affects the hold voltage, namely, the droop increases due to excessive current flowing into the capacitor 25 from such a rise in the potential V1. In addition, even if the transistor 23 completely maintains the OFF-state, a feed through wherein the sample voltage affects the hold voltage of the capacitor 25 via the gate capacitance of the transistor 23 may occur.
FIG. 2 is an explanatory view of a simulation result, which explains the droop and feed throughf in the first example of the prior art in FIG. 1. In this simulation, the uppermost signal, RF, indicates the sample signal, namely the input analog signal; and the rectangular signal, CLK, directly below indicates the sample clock. The third wave form from the top indicates the hold output. This value corresponds to the sample signal RF while the sample clock CLK is “H”. During the hold period, namely when CLK is “L”, although the value is ideally held constant at the hold voltage, it tends to drop with time due to the droop. The lowermost waveform indicates the output of the preamplifier in FIG. 1, namely, the potential V1 that is applied to the gate of the transistor 23, and shows that the influence of the sample signal RF is significant even during the hold period.
In FIG. 2, the droop is indicated by the drop in the potential during the hold period. It is shown that if the value of the hold voltage at the falling edge of the clock signal CLK is low, the variation in the hold output is small, and the value of the droop is small. But if the voltage is high, the maximum value of the droop at the time of a high hold voltage is 61 mV. In addition, feed through is indicated by a slight variation in the voltage when the clock signal CLK is “L”, or in other words, during the hold period, namely, as a slight oscillation of a frequency equal to that of the sample signal RF.
In addition, in FIG. 2, the sample signal, namely the input analog signal, is shown as a sine wave signal with a constant amplitude of 26.5 GHz, and the sample clock signal is shown as a rectangular wave signal of 1.5 GHz. Although the relation between the frequencies of the signals differs from that between the frequencies of the sample signal and the clock signal of a conventional analog/digital converter or the like, this is a typical relation wherein Ultra Wide Band communication is the field of application. In practice, the sample signal is not a continuous sine wave as shown in FIG. 2, but rather one which accommodates instances wherein a reflected wave is intermittently received even if the frequency is the same, and the voltage hold is performed on the intermittently received reflected wave by using the rising or falling edge of the clock signal.
FIG. 3 is a circuit diagram of a second example of the prior art of a sample-hold circuit. The second example of the prior art is disclosed in the following patent reference.
[Patent Reference 1] Japanese Published Patent application No. 9-130168 “Track/Hold Amplifier”
In the second example of the prior art, in comparison with the first example of the prior art, a transistor 29, which is equivalent to the pull-up circuit of Patent Reference 1 is added. The transistor 29 is intended for turning the transistors 11 and 12 OFF during the hold period, and the potential VBHck is applied to the gate thereof to turn the transistor 29 ON during the hold period. This enables the transistor 11 to be turned OFF during the hold period, thereby suppressing the influence of the variation in the sample signal on the gate potential V1 of the transistor 23, and realizing a reduction of feed through.
However, in the second example of the prior art, although the feed through is suppressed, there exists a problem in that the current source current I1 does not flow into the resistor 15 during the hold period, and compared with the first example of the prior art, the potential V1 during the hold period is increased by R1×I1, and thus the droop aggravated. In order to avoid this situation, it is effective to increase the current source current I2. However, if I2 is increased, the switching characteristics of the transistors 21 and 22, which comprise the differential transistor pair wherein current switching is performed, deteriorate, and power consumption increases. Therefore, there is an additional problem in that design parameters are restricted. Furthermore, although not only the influence of the leakage current of the transistor 23, but also that of the leak current of the transistor 21 which is connected to the capacitor 25 is considered as a cause of the droop, there remains a problem that no countermeasures thereto are taken even in the second example of the prior art.